A New PVT-Resistant Mixed-Signal Circuit Capable of Detecting Clock Glitches on IoT Devices Which Shorten the Clock Period by 0.9 ns Only

A new mixed-signal circuit chip is presented to detect clock glitches, one of fault injection attackss (FIAs), on cryptographic chips, particularly those deployed in Internet of Things (IoT) devices. In fact, IoT devices in communication often operate under strict cost, power, area constraints and physically accessible environments, making it critical of hardware security and protection against FIA. The key success of the proposed detection lies in a custom-designed delay chain being automatically tuned to approach the remaining operable clock period in the presence of glitches. Successful detection of clock glitches can then be ensured by monitoring continuously whether the clock cycle is shorter than the thresholds defined by the delay chain. The main contribution of this work is the automatic tuning of the delay chain length in an on-line, on-chip fashion to detect glitches even with varied process, voltage, and temperature (PVT) conditions. The on-line adaptivity is made possible by integrating a digital control unit that governs adaptivity and the delay chain, implemented as a mixed-signal circuit capable of effectively detecting malicious clock glitches. The proposed protection circuit was fabricated using the TSMC 180-nm process with an advanced encryption standard (AES) crypto engine serving as a test case to validate the detection capability. Experimental results demonstrate a 100% success rate in detecting glitches at operating frequencies up to 33.3 MHz, with a minimum detectable clock shortening (MDCS) of 0.9 ns caused by clock glitches, showing a state-of-the-art performance as compared to previously reported works.