Intelligent Optimization Design of GS-TSV With RDLs for Chiplet-Based Integrated System in IoT

Chiplet interconnect technology meets the need for high performance, low power consumption and miniaturization in Internet of Things (IoT) devices. To address the co-design challenge of signal integrity and thermal stress reliability within chiplet interconnect structures, an intelligent optimization design method of ground signal (GS)-through silicon via (TSV) (GS-TSV) with redistribution layers (RDLs) is developed. First, the least squares-support vector machine model is employed to map the relationship between geometrical parameters and performance metrics. Then, construct a multiobjective optimization function, and the linearly decreasing inertia weight-particle swarm optimization algorithm is applied to co-optimize. Finally, three cases are conducted to verify the feasibility and accuracy of the developed method using finite element software. The optimized return loss, insertion loss, peak temperature, and peak stress well agree with the specified targets, with the maximum relative errors of 2.75%, 1.07% and 2.76% for Case A, B and C, respectively. Eye diagram analysis shows that the optimized structure can support high speed data transmission up to 10 Gb/s, and thermal stress reliability between the array GS-TSV with RDLs and the chiplet is analyzed. Therefore, the developed method effectively optimizes the design of interconnect structures in Chiplet-based integrated system, which can promote IoT development.