A Fully Symmetric Oscillator-Based CMOS Ising Machine Architecture With Successive Approximation Sampling and Power Efficient Solution Refinement

The Ising machine is regarded as a promising computing architecture for obtaining approximate solutions to some nondeterministic polynomial time hard (NP-hard) problems. Utilizing a CMOS process, a large-scale Ising machine can be integrated to achieve enhanced energy efficiency compared to classical computing approaches. This work presents a fully symmetric, oscillator-based CMOS Ising machine architecture, which employs differential ring oscillator (ROSC) to implement spin, ensuring consistency between the theoretical framework and practical implementation. The coupled ROSC array is mathematically proven to have a Hamiltonian in the form of the Ising model, making it particularly suitable for implementing the Ising machine. A 240-spin CMOS Ising machine has been fabricated and tested. The proposed Ising machine takes a square lattice topology with four-level, reconfigurable coupling parameters with sign. Using a successive approximation sampling scheme, the Hamiltonian can be refined with the increasing iterations. The prototype demonstrates a power consumption of 26.3 $\mathrm {\mu \text {W} }$ /Spin, indicating significant energy efficiency and performance enhancement.