Design and Implementation of a Reconfigurable Modular Multiplier on FPGA

With the acceleration of the migration process to post-quantum cryptography, how to implement various post-quantum cryptographic algorithms quickly and flexibly has become an important research topic in the industry. Modular multiplication, as the core arithmetic unit for polynomial multiplication in post-quantum cryptographic algorithms, its performance and flexibility directly affect the implementation of post-quantum cryptographic algorithms. However, traditional modular multipliers mainly support modular multiplication between two variables. When the input is a constant and a variable, they have high hardware resource consumption and latency, which reduces the system performance to a certain extent. Therefore, this paper proposes a reconfigurable modular multiplier that can flexibly support modular multiplication between two variables and between a variable and a constant on the same hardware. Compared with existing modular multipliers, it has lower hardware resource consumption and higher performance.