FPGA-Based Hardware Efficient Approximate Floating-Point Multiplier With LUT-Oriented Unit

Approximate computing is well-suited for error-tolerant applications, as it improves hardware performance with only minor precision loss. Although approximate computing has advanced floating-point operations on ASIC, FPGA implementations continue to face challenges such as high power consumption and long circuit delays. To overcome these limitations, this paper introduces a floating-point multiplication framework with FPGA-fabrics that ensures accuracy in the exponent while approximating the mantissa. Initially, a purely LUT-oriented exact 3×3 multiplier is proposed as an elementary unit for the mantissa multiplication. Next, the mantissa is shortened according to a bit significance distribution analysis. To compensate for errors introduced by truncation, a leading-trailing-one structure is proposed, leveraging the inherent leading one bit in the mantissa. Finally, to improve scalability across various domains, the proposed design is extended to larger configuration. Compared with the exact multiplier of Xilinx IP, the proposed designs can achieve up to 95.43% and 39.77% improvements in power and delay, respectively. As evidenced by the performance of the scaled multiplier, our methodology demonstrates the capability to design larger-size multipliers flexibly. Compared with previous works, the proposed designs achieves more hardware savings under a similar accuracy loss.