Power-Optimized Clocking Strategies for Synchronous VLSI Systems

In modern VLSI systems low-power techniques are essential, with clock gating being a key strategy to reduce power dissipation. This paper examines the transition from traditional VLSI design challenges to modern power-efficient designs. By focusing on an 8 -bit Arithmetic Logic Unit (ALU), this study compares existing clock gating techniques and introduces a novel gated clock generation method. Results demonstrate a significant reduction in clock delay ($\mathbf{7 2 \% - 7 8 \%}$), a 24 % improvement in chip area, and a 64.27 % increase in power efficiency using the proposed method. Experimental evaluations employed 130 nm standard libraries, Verilog HDL, and ModelSim-Altera simulation tools.