Power Optimized FPGA implementation of FIR Filter using Sub Component Minimization

FIR filter design has majorly affected by three important factors in FPGA design. The reconfigurability, power efficiency and delay. the high-power consumption is one of the challenging criteria particularly in real time embedded system designs. This paper introduced a power optimized FIR filter design using minimization of usage that is resource sharing operation. The proposed design uses the sharing of filter coefficient in the process of implementation which can be designed based on the approximation method. The main structure of the design based on the approximation of coefficients and design a parallel architecture for generating product terms. The proposed design is implemented in FPGA and compared with the conventional technique of FIR filter design. The experimental results shows that this design achieves better power efficiency compared to conventional designs.