Model-Based Write Algorithm for Memristive Crossbar Arrays

In this paper, we propose a model-based write algorithm for memristive crossbar arrays employing 1 R analogswitching devices significantly improving write process efficiency over the conventional write-and-verify tuning algorithm. Leveraging a physics-based compact memristor model, we evaluate the V/2, V/3 and floating crossbar writing schemes and implement the novel developed algorithm based on the pulse time. Simulations of various crossbar sizes are conducted, assessing critical parameters including energy consumption, conductance overshoot, write time, number of iterations, and unselected cell error. We developed a versatile simulation platform that enables simulation of any SPICE-compatible memristor models, incorporating parasitic circuit elements like capacitances. The proposed algorithm significantly reduces the number of write iterations and time by half, while also lowering energy consumption and enhancing overall write accuracy.