A 50-64GHz 21.4dBm, 20.6% SE Intrinsically Linear Digital Cartesian Transmitter with 6.5° System AM-PM Distortion Using Impedance-Compensated RFDAC in 40-nm CMOS

This paper presents a 50-64GHz intrinsically linear and efficient digital Cartesian transmitter (TX). Such TX mainly consists of an impedance-compensated Cartesian RFDAC, a 4-to-1 linear power combining PA, an IQ generator, and baseband digital circuits. The low power impedance-compensated RFDAC can achieve constant source impedance for high linearity. The power combining PA provides high output power with high efficiency. Asymmetrical interstage matching network between RFDAC and PA can cancel the LO leakage of the RFDAC. The proposed digital Cartesian TX is implemented in conventional 40-nm CMOS technology. The TX demonstrates a peak output power of 21.4dBm and a peak SE of 20.6%. The AM-PM distortion is 6.5°. The INL is less than 0.1 and the DNL is between +1 LSB to −1 LSB. The TX supports 8Gb/s 16-QAM modulated signals and 3Gb/s 64-QAM modulated signals at 60GHz.