A 204GS/s 1-to-2 Analog Demultiplexer in 22nm FDSOI CMOS

A 204GS/s 1-to-2 analog demultiplexer (ADEMUX) is reported with a measured bandwidth of 60 GHz and a hold-mode isolation $\gt20 \mathrm{~dB}$ up to 67 GHz. It operates with rail-to-rail sampling clock signals up to at least 102 GHz, the highest in CMOS. A SFDR of 32 dB was measured for $11 \mathrm{GHz}, 600 \mathrm{mV}_{\text {ppd }}$ sinusoidal inputs sampled with a 64 GHz clock. Large signal operation was demonstrated by demultiplexing a 92 GBaud ($184 \mathrm{~Gb} / \mathrm{s}$) PAM-4 input into two 46Baud PAM-4 output streams sampled on opposite phases of the 46 GHz clock signal. The data path of the ADEMUX consumes 48 mW from 0.8 V, while the power consumption of the clock amplifier is 109 mW from 0.8 V and 1.2 V supplies.