110-to-140 GHz Frequency Tripler with 13% Efficiency, 7.2 dBm Psat using Adaptive Biasing and 3rd Harmonic Boosting in 22 nm FDSOI

This paper presents a high-efficiency D-band frequency tripler in 22 nm FDSOI CMOS. The operation point is chosen using drain current Taylor series derivation to boost the $3^{\text {rd }}$ harmonic (H3) adaptively. The tripler core transitions for increasing input power ($P_{\text {in }}$) from compressive to expansive behavior thanks to the proposed biasing scheme. At low $P_{\text {in }}$ of -10 dBm the tripler achieves a peak conversion gain of 11 dB thanks to step-up balun and capacitive over-neutralization. Yet, at high $P_{\text {in }}$ of 4 dBm, the $5^{\text {th }}$-order nonlinearity boosts $3^{\text {rd }}$-harmonic and enables achieving 13% peak efficiency and Psat of $\mathbf{7. 2 ~ d B m}$.