A Low-Jitter Multi-Phase Clock Generator with Skew Calibration For Time-Interleaved ADCs

This paper proposes a low-jitter clock generation system for a 12-bit, 2 GHz time-interleaved ADC. The system utilizes a 1 GHz differential sine wave signal as the input and generates four 500 MHz clocks, each with a 25% duty cycle. To correct the skew errors between the sub-ADCs, a digitally controlled delay line (DCDL) has been introduced. A skew detection circuit based on autocorrelation operates in the background, continuously monitoring the skew and adjusting the DCDL to eliminate it. The clock system has been implemented and validated using the 40nm CMOS technology, operating at a voltage of 1.1 V and consuming 19.7 mW, with the CML buffer being the largest power consumer at 11.5 mW. Simulation results indicate that the system achieves a jitter of 25.4 fs. Following skew calibration, the ADC achieves SNDR and SFDR values of 63.05 dB and 73.97 dB, respectively.