Enhanced JPEG Decoding Using PIM Architectures with Parallel MCU Processing

The JPEG format can compress digital images by reducing file sizes while maintaining visual quality. However, decoding JPEG images can become a bottleneck when large-scale image processing is essential. Numerous studies have focused on accelerating JPEG decoding, while only one has explored processing-in-memory (PIM) architectures to mitigate data bottlenecks by integrating computational units into memory. The solution UPMEM PIM enables large-scale parallel processing via DRAM processing units (DPUs). Existing PIM-based JPEG decoders do not employ DPU-level parallelism fully due to the structural constraints of UPMEM PIM, requiring each DPU to handle at least one image. Thus, supported image resolutions are limited, reducing decoding speed. Due to the difficulty of implementing hardware thread synchronization, image-block misalignment can occur, creating discrepancies from the original image. This paper proposes a novel PIM decoder (NPD) exploiting the parallelism of multiple DPUs, performing Huffman decoding on the host CPU, eliminating dependencies between image blocks, and enabling distributed processing across DPUs. This approach increases the supported image resolution, improves decoding speed, and enhances decoding quality by reassembling multiple blocks into a single image without synchronization. The performance evaluations on UPMEM PIM servers using lowand high-resolution image datasets compare the decodable image resolution, execution time, and decoding quality of the decoders. The NPD processes images with resolutions up to 3.57 times higher than those of the existing decoder, reducing execution time by 4% to 85%. Comparing the decoded results with the original images using the peak signal-to-noise ratio and structural similarity index measure confirmed that the NPD offers higher and more stable decoding quality.