Dual-Mode PUF and TRNG Design with Ring Generator on 180nm CMOS

Lightweight and efficient designs of physical unclonable functions (PUFs) and true random number generators (TRNGs) are essential for small embedded devices to enable cryptography applications with secure authentication and randomness. Separate designs of PUFs and TRNGs may incur high costs in hardware, power consumption, and design complexity, as entropy extraction and control mechanisms vary. A compact and robust design combining both functions can significantly reduce the overheads. This work presents a methodology for unifying the design of PUF and TRNG by linking multiple entropy extraction cells to a robust back-end obfuscation using a ring generator. The synthesized design on 180 nm CMOS technology costs a small hardware footprint of $95.95 \mu ~\mathrm{m}^{2}$ and a minimal energy efficiency of $\text{2 3. 3 1 p J} / \text{b i t}$ at $\text{1 0 0 ~ M b p s}$ throughput. Additionally, the implementation on FPGA validates the performance of both the PUF and TRNG modes. In PUF mode, the system demonstrated nearly ideal uniqueness and uniformity, achieving 49.98 % and 50 %, respectively. The random numbers generated in TRNG mode successfully passed the National Institute of Standards and Technology (NIST) SP800-22 random test.