A 7mW 22 GHz Frequency Divider Chain by 2048 using CML, TSPC and CMOS Logic in 22FDX

This paper presents a low-power frequency divider chain with a division ratio of 2048 realized in a 22nm FDSOI CMOS technology. To optimize the power consumption, yet achieve high-speed operation, we realize the first stages using the CML logic, while the subsequent stages are implemented in TSPC logic and finally, the lower speed stages use the classical CMOS logic. Thus, we achieve an optimally low power consumption as we advance along the frequency divider chain from 22GHz at the input down to 10.74MHz at the output. The entire chain dissipates only 8.75mA from a single 0.8V supply, distributed as follows: the active balun at the input consumes 4 mA, while the frequency divider chain itself draws only 4.75 mA. The chip is inductorless and thus very compact. The presented chip occupies a minimal area of only 510 by 360 μm including pads.