Split-Gate 2T Gain Cell Memory for Reducing Capacitive Coupling and Sneak Current

The two-transistor (2T) gain cell is a promising candidate for embedded dynamic random access memory (eDRAM) applications, offering a compact cell size along with fast and non-destructive read operations. However, it remains vulnerable to storage node (SN) voltage degradation by capacitive coupling in a single cell, as well as sneak path and IR drop issues in array structures. This study proposes a split-gate 2T gain cell that employs a split-gate transistor as the read transistor, effectively addressing both cell-level and array-level challenges. It suppresses capacitive coupling by physically isolating the SN from the bitline (BL). Furthermore, it mitigates sneak path and IR drop issues by blocking current between BL and read-word-line (RWL).