A 58.9fs-Jitter Fractional-N Digital PLL Using a Double-Edge Variable-Slope DTC

This work presents a fractional-N digital PLL achieving low-jitter by leveraging the combination of a XOR frequencydoubler and a power-efficient double-edge variable-slope digital-to-time converter (DTC). The prototype demonstrates 58.9fs jitter and -61.8 dBc fractional spur at 9.25 GHz, with 18.3 mW power and 125 MHz input reference frequency.