A 31.5-36 GHz Low-Spur Gain-Boosting Charge-Sharing Locking PLL with 54fs Jitter

We propose a gain-boosting (GB) charge-sharing locking (CSL) PLL that achieves both ultra-low jitter and low reference spur. The GB-CSL mechanism reads the charge residue of CSL via an ADC, amplifies it digitally, and precharges it back via a DAC with a small charge-sharing capacitor Cshare coupled to the LC-tank. This significantly enhances the PLL bandwidth $f_{\text{BW}}$, resulting in low rms jitter while minimizing load modulation to the LC-tank. Implemented in 28-nm CMOS, the $\sim 33-\text{GHz}$ PLL achieves 54 fs rms jitter and a low reference spur of -66 dBc, while consuming 14 mW.