Comparative Analysis of High-Speed Power Efficient 4:2 Compressor using Cadence Tool

The development of new digital circuit designs is essential to address the increasing demand for high-performance and energy-efficient computing. Compressors play a key role in mathematical circuits and digital signal processing by streamlining complex calculations. In particular, multipliers depend on compressors to enhance their efficiency. In modern technology, digital multipliers and compressors help to reduce partial product iterations, leading to improved computational performance. This manuscript focuses on evaluating and comparing high-speed, low-power 4:2 compressors. Among various architectures, the proposed 4:2 compressor stands out for its ability to enhance both speed and power efficiency. The simulation of this compressor is verified using the 45nm gpdk based CMOS Cadence Virtuoso tool. Compared to existing approaches, the proposed model is optimized to minimize both power consumption and latency.