Circuit Design and Implementation of Low Power and High Efficiency Decoder

In VLSI design, Reversible logic is popular. This paper proposes a technique allowing the designer to exploit Reversible logic in their decoder circuits. Feed-back-Fan-out combination is not acceptable under logical reversibility restrictions. It is meant for applications in varied areas such as computer graphics, high-performance computing, and Nanoscale. A Reversible logic circuit in terms of energy consumption is presented in this paper. It is mainly important for the minimization of power supply needs. This system has created various decoder circuits, such as the 2 to 4,3 to 8 ,4 to 16 Decoder.