A 65-nm CMOS Downconverter-Less Clock Generator Architecture Using Voltage Stacking of Oscillator and Frequency Dividers for Scaling-Friendly IoTs

The demand for high energy efficiency in IoT devices continues to increase, necessitating the development of low energy consumption techniques to enhance the computation performance of these devices. In this study, we present a CMOS clock generator that operates at high operating voltage, achieves low frequency, and exhibits low power (LP) consumption, thus obviating the need for scaling-unfriendly step-down converters. The avoidance of step-down converters, which require passive components in their design, facilitates the development of scaling-friendly IoTs. The architecture of the prototype chip is composed of a voltage stacking and charge recycling design, which is achieved by the implementation of stacked oscillator and multiple frequency dividers in a configuration. The fabrication of the prototype chip is conducted using a 65-nm CMOS process. This work presents two configurations that are based on the concept of voltage stacking. The first configuration prioritizes LP consumption, yielding a clock generation of 2.09 Hz with a power of 0.22 nW at a voltage supply of 1.2 V and an operating range of 1.2–2.2 V. Notably, this configuration represents the lowest power achieved at a foundry-recommended nominal voltage in a sub-10-Hz clock generator. Another configuration is oriented toward generating low-frequency output signals, and the test chip attains an output frequency of 0.079 Hz and a supply voltage range of 0.88–1.3 V. The proposed architecture exhibits potential benefits in advanced technology nodes, particularly in the context of technology scaling.