Enhanced Low-Power Approximate 8-Bit Multipliers for Image Processing Based on Optimized 4:2 Compressors and Adders

Approximate computing has emerged as a promising solution for enhancing power and area efficiency in applications where exact precision is not mandatory. This paper proposes a set of novel 8-bit approximate multiplier architectures that incorporate two custom-designed approximate full adders (LFA1 and LFA2) along with a simplified 4:2 compressor. These components are strategically integrated to minimize hardware complexity while delivering acceptable accuracy for error-tolerant domains such as image processing and machine learning. The simulation results demonstrate up to 16.18% reduction in area, 28.19% savings in power consumption, and modest variations in delay, highlighting the effectiveness of the designs. By embracing a practical trade-off between accuracy and efficiency, the proposed multipliers provide a highly scalable and energy-efficient solution for modern VLSI systems, addressing the increasing demand for low-power digital circuit design.