Micro-Architecture Design and Analysis of AXI Enabled SHA-3 Hardware Accelerator for a RISC-V Based SoC

Hash algorithms typically find applications in message authentication, digital signatures, pseudo random generators, and derivation of crypto keys etc. Focusing on the Keccak SHA-3, which had been standardized by NIST as FIPS-202, our research emphasizes the intricacies of design, development, and analysis of an accelerator. This article delves into the micro-architecture of the Keccak SHA-3 hash function, leveraging a sponge construction methodology for hash value computation. Two design approaches have been illustrated for the SHA-3 accelerator: i) Fully iterative approach, ii) Pipelined design. The accelerator supports all four SHA-3 variants (224, 256, 384, and 512). The accelerator is enabled with AXI bus interface registers and integrates with a RISC-V based System-on-Chip (SoC). In order to validate SHA-3 hashing operations in the RISC-V based SoC, executed application codes written in C language, underscoring the practical utility of the developed accelerator. Modules are implemented in Verilog RTL have undergone rigorous verification using NIST test vectors at simulation level. Validation on the Xilinx Virtex UltraScale VCU 108 FPGA, coupled with PCIe connectivity, underscores the robustness of the SHA-3 accelerator. Further, a SHA-3 Accelerator integrated into a RISC-V based SoC, deployed on Xilinx Virtex UltraScale VCU 108 FPGA devices, executes hashing application software. This paper analyzes area utilization, frequency of operation, and throughput (Gbps) for the proposed architectures and is presented. Iterative SHA-3 design achieves a commendable throughput of 21 Gbps, while pipelined design surpass 27 Gbps on Xilinx Virtex UltraScale VCU 108 FPGA devices.