An Optimized FPGA-Based FDIR System for Sensor Fault Detection in Satellite Attitude Estimation

Sensor failure is a major issue in satellite attitude estimations, which widely employs the Inertial Measurement Unit (IMU). The failure of this sensor often causes severe accidents and may lead to mission failures. To solve this problem, a Fault Detection, Isolation, and Recovery (FDIR) was proposed, which integrates an adaptive unscented Kalman filter (AUKF), a radial basis function (RBF) neural network for fault detection, and a QUEST-based estimator. However, the FDIR algorithm is computation-intensive, taking up valuable hardware resources and slowing down processing speed, which presents a challenge for real-time attitude control systems. This paper addresses these challenges by optimizing FDIR hardware implementation through reshaping, parallelism, and pipelining to reduce computational load and latency while enhancing efficiency and processing speed. It also ensures high accuracy and resilience against sensor failures. The proposed design is divided into four stages. These stages are optimized through reshaping, parallelism, and pipeline processing on the FPGA. Compared to the GPU implementation, the FPGA-based FDIR implementation offers faster processing speed and reduces the power consumption while maintaining valid estimation under faulty conditions.