SCiMA: A Systolic CiM-Based Accelerator With a New Weight Mapping for CNNs—A Virtual Framework Approach

Efficient execution of deep convolutional neural networks (DCNNs) on von Neumann platforms has significantly encountered the memory wall. Computation-in-Memory (CiM) aims to integrate computation and storage by performing analog dot product operations within memory cells. Despite advancements, CiM-based architectures still face bottlenecks in transferring input and partial result data to and from CiM units. To address this, a programmable CiM-based Systolic Accelerator (SCiMA) is proposed, featuring an array of Tiles with deep systolic dataflow within architectural levels, providing a scalable and efficient dataflow for DCNN inference. To reduce data movement more efficiently for convolutional layers, which are feature-dominant, proposed inter- and intra-crossbar weight mapping strategies aim to minimize Tile buffering requirements and enhance data reuse. For dense layers, which have the highest weight dominance, Sparse SCiMA leverages structured pruning to exploit sparsity and enhance area efficiency. Additionally, a virtual SystemC-Python framework is introduced to compile CNN applications onto SCiMA and to explore and evaluate architectural, power, and timing aspects using back-annotated circuit-level information. This framework leveraged matrix-based emulation of the analog computations to calculate the impact of non-idealities in results, thus enabling efficient emulation. Experimental results demonstrate that the proposed CiM-based systolic dataflow and weight mapping for convolutional layers improve computation cycles and data movement by 62% and 57%, respectively, compared to the conventional shared bus structure and weight mapping used in state-of-the-art architectures. Overall, SCiMA improves throughput and power efficiency by 38% and 42% on average, respectively, compared to other architectures. Sparse SCiMA reduces the area and power overhead by 43% and 40% respectively compared to SCiMA.