The JPL Snapdragon Co-Processor: A Compact High-Performance Computer for Spaceflight Applications

Following in the footsteps of the resounding success of the Ingenuity Mars Helicopter which was powered by a Qualcomm® Snapdragon^TM 801 system-on-chip (SoC), the Jet Propulsion Laboratory has continued its investments into high-performance spaceflight computers based on Qualcomm's Snapdragon line of SoCs. One significant achievement of these efforts is the development of the JPL Snapdragon Co-Processor (SCP), a small form-factor computer for spaceflight applications featuring the automotive-grade Snapdragon SA8155P SoC. The technology readiness level (TRL) of the SCP was raised to TRL-6 in January 2024. The SCP is currently being included in two upcoming CubeSat-based on-orbit technology demonstration missions and is under consideration as a computer vision processor for missions up to and including class-B. The Snapdragon SA8155P features an octa-core Arm® CPU cluster with four Cortex® A-76 and four Cortex A-55 cores, a graphics processing unit (GPU) capable of 898 GFLOPs (32-bit floating-point), and a cluster of 4 Hexagon™ DSP cores. The SCP board is outfitted with 16 GB of RAM, 128 GB of non-volatile Flash memory, and 2 Mb FRAM. The external interfaces of the SCP are two USB 3.1 Gen2 ports, a 4×4 lane MIPI Camera Serial Interface connector, and a 200-pin space-grade mezzanine connector featuring three total PCI Express lanes, an RGMII interface to support Gigabit Ethernet, and low-speed UART, GPIO, JTAG, and SPI connections. To utilize the interfaces on the mezzanine connector, JPL has developed a variety of custom carrier cards for the SCP, ranging from the advanced and high-performance line of Swift Processor Modules to a dedicated SCP carrier card for CubeSat applications. In this paper, we present a detailed overview of the SCP design, its capabilities, and its interfaces to the spacecraft bus. We describe the available options to integrate the SCP into a spacecraft using the currently available and in-development carrier boards as examples. We comment on the software support and past and future JPL software benchmarking and porting efforts. Finally, we comment on the TRL-6 test campaign and give a brief outlook of the future of the SCP for JPL missions and the wider spaceflight community.