Identifying Design Challenges in Analog Circuits due to Device Non-Idealities at Cryogenic Temperatures

This work presents a detailed analysis of the impact of MOS device performance on circuit metrics at cryogenic temperatures. An experimentally proven, industry standard compact model is calibrated to match the performance of the corresponding devices from ST Microelectronics 28 nm (STM28) PDK. The temperature related parameters of this model are then calibrated with experimental data at cryogenic temperatures, available in the literature. This model is then used to explore a Strong-Arm latched comparator, a 4-bit Flash ADC and a ring oscillator to study temperature-dependent performance trends. We point out certain key concerns which necessitate additional design effort and area/hardware overhead required to achieve the desired specifications at cryogenic temperatures.