On Internally Tagged Instruction Set Architectures

Traditional instruction set architectures rely on instructions specifying data types to execute the correct operations, e.g., integer or floating-point addition. This duplication of instructions for each data type increases the number of opcodes needed in the architecture and encoding space usage. In this paper, we revisit the tagged architecture, where the data type is stored adjacent to its value. Polymorphic instructions account for the data’s type to perform the correct operation. We show that limiting type-tracking to within the processor exclusively provides many of the benefits of the original tagged architectures without the associated overheads. We show that designing an instruction set architecture with tagging can provide significant benefits to the efficiency of the instruction set at a negligible cost. As proof of concept, we analyze the application of tagging to the RISC-V RV64GC architecture. We see a 40.84% reduction in needed opcodes and a 25.72% reduction in encoding space usage.