Investigating the Charge Trapping Behavior and Enhancing the Memory Window of Silicon Channel Hf0.5Zr0.5O2 FeFET With SiO2/HfO2/SiO2 Gate Side Interlayer

We demonstrate a Si-channel Hf0.5Zr0.5O2 FeFET that achieves a record-high memory window (MW) of up to 19.4 V, together with better data retention. This advancement is realized by inserting the SiO2/HfO2/SiO2 (SHS) gate interlayer between the metal gate and the ferroelectric Hf0.5Zr0.5O2 layer. The gate interlayer effectively retains the charges injected from the metal gate. The influence of SiO2 thickness on reliability was investigated. We found that increasing the thickness of the SiO2 gate interlayer led to the degradation of endurance. The retention loss shows no significant improvement. We further discuss the spatial distribution and quantity of gate-injected charges by varying the thickness of each SiO2 layer in the SHS gate interlayer. The charge-trapping behaviors of gate-injected electrons and holes in the SHS gate interlayer are asymmetric. For data retention, two different mechanisms contribute to data retention loss: the reduction in threshold voltage after the erasing process results from the de-trapping of gate-injected electrons, while an increase in threshold voltage after the programming process is attributed to the movement of gate-injected holes. This work provides new insights into the gate-injected charges and data retention in the FeFETs with a gate interlayer.