Tag-based Two-path Data Cache Efficiently Achieves Cache Side Channel Attacks Immunity

To mitigate the threat of cache side channel attacks to IoT embedded processors, a novel secure data cache structure called TPDC for tagged memory is proposed. It handles accesses on isolated paths, monitors legality at hardware level based on security tags, balances access times to eliminate leakage risks. It achieves fine-grained in-process isolation together with taggedmemory and access time isolation in cache. Implemented by hardware, it has less software cost. Evaluated on an out-of-order RISC-V processor, it can resist Spectre and Meltdown attacks. Compared to ordinary designs, its miss rate and access time overheads are $0.07 \%$ and $7.24 \%$ respectively.