Design and Implementation of Carry Look-Ahead Adder Using PTL with Comparative Analysis Against Transmission Gate Logic

In modern VLSI design, speed, power consumption, and area are key constraints of modern-day VLSI design. There exist several styles of logic that address these design constraints, including Dynamic CMOS, Static CMOS, Reversible Gates, Transmission Gates (TG), Pass Transistor Logic (PTL), and new- fangled ones like Gate Diffusion Input (GDI). The Implementation and design of a 4-bit Carry LookAhead Adder (CLA) employing Pass Transistor Logic (PTL) and the Transmission Gate (TG) style are presented here. PTL is effective in reducing the number of transistors, thus producing a smaller area and lower power consumption, hence it is used for low-power and small- area design. PTL reduces the number of transistors by 58.82% and optimizes the power consumption by 28.14% compared to TG. However, TG is better in terms of performance speed and delay time, reporting a 48.5% improvement over PTL in delay, providing greater signal integrity and more speed and reliability. Cadence Virtuoso was used to simulate and model all the designs to accurately analyze transistor count, delay, and power consumption.