A Novel 5-Tap Loop-unrolling DFE Equalizer Circuit for 12.5Gbps SerDes

We propose a novel 5-Tap Loop-unrolling DFE equalizer circuit for 12.5Gbps SerDes, which employs a half-rate 5- Tap architecture as well as the Loop-unrolling technique to enhance the overall equalization capability and reduce the BER to improve the quality of eye diagram. At a half-rate of 6.25Gbps, the sampler can sample the data normally, the DFE increases the eye height from 286.184mV to 361.143mV and 354.770mV, the spreading degree from 36.4% to 60.9% and 59.8%. The area of the overall circuit was 0.008 mm2, and circuit power consumption is 8.453mW.