DCiROM: A High-Density Fully-Digital Compute-in-Read-Only-Memory Macro for Energy-Efficient Task-Level DNN Inference

Compute-in-memory (CiM) is a promising approach to alleviating the von Neumann memory wall bottleneck in data-intensive tasks. As a candidate to build CiM, static-random-access memory (SRAM) has become popular in accelerating deep neural networks (DNNs) because of its mature fabrication support and high flexibility. However, SRAM-based CiM suffers from low memory density, resulting in frequent weight reloading and increased power consumption during end-to-end inference tasks. Recently, read-only-memory (ROM)-based analog CiM (ACiM) has demonstrated the potential to deploy all DNN weights on-chip by leveraging high-density ROM. It may also achieve encouraging flexibility by exploiting the synergy between a small SRAM and a big ROM. Nevertheless, it faces challenges in achieving high computing density due to limitations in analog-to-digital converter (ADC) performance. Meanwhile, digital CiM (DCiM) improves computing density but incurs significant energy and area overhead due to the adder tree. To address these challenges, this paper proposes the first fully digital and flexible compute-in-read-only-memory (DCiROM) design approach. On the one hand, DCiROM introduces a novel ROM-logic fusion CiM that reduces the CiM area by 51% while maintaining high memory density and computing performance. On the other hand, DCiROM achieves high flexibility with minimal area overhead by proposing two innovative multiply-and-accumulate (MAC) resource-reusing techniques. This work has implemented a DCiROM chip with 3024Kb ResNet-56 parameters using a 65nm CMOS technology. This macro achieves 6.9-29.5x higher normalized FoM (memory density x computing density) than the state-of-the-art CiM works. Additionally, it reduces energy consumption per image inference by 2.9-9.9x compared to SRAM-based CiM works when off-chip access is considered.