Analysis of Fractional Spurs in a DTC-Assisted ADPLL Exploiting Crystal-Oscillator Waveform With Harmonic-Based Digital Predistortion

This brief analyzes nonlinear effects in digital-to-time converters (DTC) operating within the sinusoidal voltage regime of a crystal oscillator (XO), prior to its final conversion into a programmable delayed clock. A detailed theoretical framework models the intrinsic nonlinearities, and a harmonic-based (HB) digital predistortion (DPD) technique is propose to mitigate them. The study explores three key aspects: 1) the intrinsic INL characteristics of the DTC, 2) the interaction between DTC nonlinearity and periodic modulation within the ADPLL feedback path, and 3) practical implementation strategies for HB-DPD. Furthermore, a new fractional spur estimation is proposed and validated through behavioral modeling and system-level simulations. Results demonstrate that HB-DPD effectively compensates for the DTC nonlinearities, with performance improving as higher-order harmonics are incorporated. Simulations confirm that applying up to fourth-order harmonic compensation limits the peak-to-peak INL within ±1 LSB (266fs) and suppresses in-band fractional spurs below −70 dBc, closely matching theoretical predictions. These findings confirm the effectiveness of HB-DPD in enhancing the linearity and spectral purity of high-performance fractional-N PLLs.