A High Sensitivity Serial-Path RF Energy Harvester in 65nm CMOS Technology

This paper presents a high-sensitivity RF energy harvester utilizing a novel circuit configuration with a series connection. Optimization of the CMOS switches, particularly in the off state, enhances the power conversion efficiency (PCE). To maximize the voltage amplitude at the MOSFET's gate node of the rectifier, the input power from the antenna is resonated through a parallel-connected capacitor bank. The harvester is designed and laid out using 65nm CMOS technology, occupying a chip area of 390 × 220 μm². The proposed system achieves over 20% RF-to-DC PCE across a 14 dB input power range, with a peak efficiency of 26.5% and a sensitivity of -29 dBm at an output voltage of 0.5V.