Spin-Orbit Torque MRAM TCAM for Tested Model With Cross-Layer Three-Level Reliability Amortizing

Due to the low-tunnel magnetoresistance ratio (TMR) and susceptibility to process variation of industrial spin-orbit torque-magnetic random access memory (SOT-MRAM), the search reliability of previous SOT-based ternary content addressable memory (TCAM) is low. This article analyzes search errors affecting the processing reliability of SOT-TCAM at both device and circuit cross-layer levels and proposes three-level fine-amortizing (TLFA) methodologies to address these issues. To achieve ideal performance based on a practical device, this article proposes a six transistors and four MTJs (6T-4Ms) SOT-TCAM search cell with latch sense achieving in situ high reliability. This design is evaluated based on an industrial 40-nm CMOS technology node and 88-nm perpendicular SOT-MTJ backend-of-line (BEOL) process. The voltage swing of the match line ( $\Delta {{V}_{\text {ML}\_{\text {SW}}}}$ ) is increased to $8.5\times $ compared with the previous SOT-TCAM and soft error rate (SER) reaches <0.1% with high reliability under ${V}_{\text {DD}} =0.8$ V. The energy consumption reaches 3 fJ at ${V}_{\text {DD}} =0.8$ V. With the TLFA methodologies, the search reliability is increased confronted with extreme conditions when ${V}_{\text {DD}}$ drop to 0.6 V.