System-on-Chip Test and Characterization: A Review

Integrated circuit (IC) test is a critical component in ensuring product quality, reliability, and cost control within the IC manufacturing process. Due to the increasingly integrated nature of system-on-chip (SoC) designs, the demand for studying mixed-signal test in SoC dominates the chip test nowadays. While numerous test methodologies, such as structural test, $I_{\mathrm {DDQ}}$ test, static or dynamic parameter characterization, and data processing, have been extensively studied, most of these focus on isolated test items for efficiency or fault coverage. Very limited work has been conducted on efficiency analysis across the entire manufacturing process. To address these limitations, this review synthesizes guidelines to reduce test costs while maintaining fault coverage throughout the entire test paradigm. Based on applicability, SoC test methods are primarily divided into three categories: direct test with automatic test equipment (ATE), test with design for test (DFT) technology, and failure analysis methods. To further assist researchers and engineers with diverse needs, these methods are subclassified by test objectives: rapid assessment, comprehensive diagnostics, and predictive analytics. Additionally, we introduce a novel metric, the extra information gain cost (EIGC), to evaluate the efficiency throughout the entire test process. Finally, this review highlights emerging research directions, such as aging prognosis and test in advanced packages.