Factors Influencing the Power Cycling Lifetime of Paralleled IGBT Chips

In this paper, the influence of device parameters spread on current sharing during power cycling test is investigated. The contribution of the asymmetry of thermal paths below individual chips to the distribution of temperature among paralleled chips in a module is also investigated. When paralleled, the IGBT chips share conduction losses based on their saturation collector-emitter voltages (VCEsat). They also share switching losses based on their gate threshold voltage (VGEth) and trans-conductance (gm). A baseplate-less IGBT module with two paralleled chips per switch was subjected to power cycling test using two approaches: by heating it with only conduction losses (classical DC test) and by heating it using both conduction and switching losses (switching-mode test). It was found that the most important parameter influencing lifetime in this module was the asymmetry in thermal paths under individual chips. Both DC-mode and switching-mode tests resulted in similar lifetime. In both cases, devices failed by either solder delamination or bond wire lift-off.