Synaptic Characteristics Dependent on Gate-Insulator Structural Properties of Low-Power Hf-ZnO Thin-Film Transistors

We present a study on the gate-insulator structure dependent on the weight-update and retention characteristics of low-power synaptic thin-film transistors (Syn-TFTs) with a hafnium-doped zinc oxide (Hf-ZnO) channel layer. For this, the pulsed characteristics of fabricated Syn-TFTs are monitored. To achieve the memory behavior of the Syn-TFT, a charge-trap layer (CTL) is used, which is deposited with HfO2 between a blocking oxide (B-OX) and a tunneling oxide (T-OX). Here, as decreasing the thickness of T-OX for the case of a single CTL, when the positive programming pulses are continuously applied to the gate terminal, electrons within the Hf-ZnO channel are relatively easy to be trapped to the CTL, leading to the improved weight-update characteristics (e.g., a programming speed). However, it is also observed that the retention characteristics (e.g., retention time) for applying a constant read voltage ( $V_{\text {read}}\text {)}$ are poorer because of a narrower energy barrier caused by the thinner T-OX, which can easily escape toward the channel layer. So, a tradeoff relation between the weight-update and retention characteristics is suggested. For overcoming this tradeoff relation, the double CTL (D-CTL) structure can be employed. For the fabricated Syn-TFT with this D-CTL structure, it is found to be a faster programming speed as well as a longer retention time of $1.3\times 10^{{7}}$ s. This is due to the increased number of T-OX, which has two energy barriers, resulting in the difficulty of the electron detrapping to the Hf-ZnO channel.