Area-Efficient and Low-Power 8T Compute-SRAM Bitcell Design for Digital Compute-In-Memory Macros in 22nm CMOS

This brief presents a novel compute-SRAM bitcell design capable of performing 1-bit digital multiplication for digital compute-in-memory (DCIM) macros. Unlike the conventional approach, which requires 10 transistors (6T SRAM + 4T NOR), the proposed bitcell achieves the same functionality with only 8 transistors. This is accomplished by efficiently embedding a NOR gate into the latch pair of the traditional 6T bitcell through the addition of two transistors. The design enables efficient in-bitcell compute operations, achieving a 37.5% reduction in area and a 41.5% reduction in leakage compared to the 10T counterpart. Moreover, the proposed bitcell maintains robust stability in terms of write and hold static noise margins, thanks to the sizing strategy and gate overdrive. To validate the design, a 64× 64 DCIM macro was fabricated using a 22nm CMOS process. The macro demonstrates a peak energy efficiency of 126 TOPS/W at INT4 precision under a 0.55 V supply.