Noise Performance Study of FPGA-based and Analog Chaos Oscillator Synchronization

This article is devoted to studying the synchronization noise immunity of chaos oscillators implemented as analog circuits as well as the chaos oscillators implemented in the field-programmable gate array (FPGA) that exhibit similar behavior to their analog counterparts. The increasing use of analog and FPGA-based chaos oscillators for secure communication applications such as security improvement and information carriers lead to the idea of utilizing both oscillators in designing a chaos-based data transmission system. The hybrid analog-discrete implementation of chaos allows for more complex modulation schemes for wireless sensor networks. The core of such an approach is the possibility of synchronizing analog chaos with its discrete counterpart implemented on the FPGA. As data transmission is done in the wireless channel, the noise immunity of such synchronization is crucial to investigate, which is the focus of this work.