Architectural Exploration and Performance Enhancement of the CVA6 RISC-V Core Using the Gem5 Simulation Framework

As embedded devices continue to proliferate in applications ranging from IoT to edge computing, optimizing SoC architectures like CVA6 for performance and efficiency has become increasingly critical. This study not only evaluates the CVA6 architecture but also introduces a novel, scalable methodology for design space exploration, applicable to a wide range of SoC designs. A high-accuracy CVA6 model was developed using the gem5 simulator, achieving less than 5% error in the RISC-V microbenchmark suite and MiBench suite in both the system simulation (bare metal mode) and the full system (FS) modes. Through this model, we systematically analyzed CVA6’s architectural choices and their impact on performance and resource utilization. To further enhance the architecture, we integrated machine learning algorithms to optimize performance and resource efficiency. This approach resulted in two distinct optimized models: a resource-efficient variant that reduced resource consumption by 12% with only a 0.2% decrease in RMS micro-benchmark IPC, and a performance-optimized model that improved performance by 29.5% while increasing resource usage by just 4.20%. Our findings not only provide a deeper understanding of CVA6’s performance characteristics but also demonstrate the effectiveness of machine learning in architectural optimization. This paper details the evaluation methodology, experimental results, and key insights, offering a framework that can be generalized to other SoC designs. This work connects architectural analysis with machine learning-based optimization, offering useful insights for future research and development of embedded systems. This work could impact the design of next-generation SoCs, paving the way for smarter, faster, and more efficient solutions for cutting-edge applications.