A 7-bit 1.41-GS/s 2-bit/Cycle Precharge-Advancing SAR ADC With Fast Discharge Comparator

A compact, high-speed 2-bit/cycle prechargeadvancing SAR ADC is proposed. By leveraging an advanced clock timing scheme, the precharge operation of the reference DACs no longer takes extra time but is completed within the sampling period. In addition, a three-stage comparator employing fast discharge technique further enhances conversion speed. The proposed redundancy setting ensures robust ADC performance by correcting errors during operation. Fabricated in a 22nm CMOS process, the 7-bit prototype ADC operates at a 1.41 GS/s sampling rate under a 1V supply, achieving an SNDR of 39.6 dB at Nyquist frequency and a FoM of 23.5 fJ/conversion step, with a total power consumption of 2.59mW. The proposed architecture achieves the highest conversion speed among state-of-the-art single-channel 6–8-bit SAR ADCs.