Holistic Memory DFT Partitioning Using a Convolution-Based Algorithm

The number of embedded memory instances within complex System-on-Chips (SoC) can be exceptionally high, occupying up to 80% of total Design-for-Test (DFT) area [1]. Designers aim to achieve an efficient Memory Built-in Self-Test (MBIST) strategy while minimizing the impact on the overall design. However, multiple restrictions and constraints must be considered, posing significant challenges from a DFT standpoint. This paper presents a novel convolution-based algorithm that offers enhanced performance and allows dynamic control over various partitioning requirements, while integrating all restrictions. When considering test time, silicon area, and routing distance together, the proposed algorithm outperforms traditional partitioning methodologies.