Arithmetic Logic Unit using 4-bit Vedic Multipliers with Multiplexers

This paper designs an 4-bit Arithmetic Logic Unit (ALU) based on multiplexers in order to construct Vedic multipliers in Verilog HDL. The Urdhva Tiryakbhayam Sutra, based on the 'Vertically and Crosswise' approach, generates partial products in parallel and makes multiplication faster and reduces hardware complexity. Along with multiplication, the ALU is also performing addition, subtraction, logical shifts, and bitwise operations. The optimized design have been simulated and synthesized with the use of industry-standard tools to maximize the utilization of resources in computation.