Design of Advanced Encryption Standard using Verilog-Hardware Descriptive Language

The critical role of encryption in securing electronic communication has led to the development of the Advanced Encryption Standard (AES), known for its adaptability in key sizes and its efficient encryption of 16-byte data blocks. Implementing AES in Verilog significantly improves performance over the older Data Encryption Standard (DES), which was constrained by a 56-bit key. AES, particularly in its AES-128 and AES-256 variants, now serves as a cornerstone in protecting sensitive digital information from unauthorized access. This paper resents an implementation of the AES using Verilog, addressing the limitations of the DES with its fixed key size. The methods involve designing and testing AES algorithms on hardware, leveraging Verilog to enhance encryption efficiency and security. The results demonstrate successful implementation of AES-128 and AES-256, providing robust data protection for 16-byte blocks. Findings highlight the significant improvement in securing sensitive information against unauthorized access and cyber threats. This work underscores the importance of AES in modern encryption and showcases the role of Verilog in optimizing hardware-based encryption solutions.