Learning of Information Bottleneck LDPC Decoding Operations with Genetic Algorithms

Physical layer signal processing presents significant challenges in military communication systems, where robust systems must retrieve data efficiently and rapidly. Therefore, this research focuses on the decoding of powerful low-density parity-check (LDPC) codes. Conventional LDPC decoders often become bottlenecks because they use cumbersome high-precision real number arithmetic. Recent approaches from the literature use compressive information bottleneck methods to reduce this complexity. They rely on integer messages and simple look-up operations, easing software implementations. Implemented on a chip, however, information bottleneck decoders, still need many logical gates to synthesize the decoding operations. As countermeasure, we directly utilize the bit-level representations of the exchanged messages. We propose to learn mutual-information-maximizing decoding circuits directly using genetic algorithms, instead of designing look-up tables and synthesizing them with elementary logical gates afterwards. Experimental results demonstrate that the proposed LDPC decoders outperform traditional suboptimal decoders, such as the min-sum decoder, in terms of bit error rate. This paper was originally presented at the NATO Science and Technology Organization Symposium (ICMCIS) organized by the Information Systems Technology (IST) Scientific and Technical Committee, IST-209-RSY - the ICMCIS, held in Oeiras, Portugal, 13–14 May 2025.”