Joint Partial Response Equalization and Multiplication-Free Error Corrector for Beyond 200-Gb/s Intra-DCIs

We propose a multiplication-free error corrector (MF-EC) to suppress the error propagation resulted from $1 /(1+D)$ decoder in a $256-\mathrm{Gb} / \mathrm{s} \mathrm{PAM}-4$ system. The proposed MF-EC achieves the same performance as MLSE at the KP4-FEC threshold.