Reconfigurable and Hardware-Efficient KECCAK Architecture with SHAKE Integration and Dynamic Input Processing for Post Quantum Cryptography

The Federal Information Processing Standard (FIPS) 202 standardizes the SHA-3 cryptographic hash algorithm. This paper presents a reconfigurable pipelined hardware architecture for the SHA-3 family, compatible with all four SHA3 modes and two SHA-3 extendable-output functions (XOFs), identified as SHAKE128 and SHAKE256. The proposed design enables the processing of variable input data directly in hardware using ASCII representation of characters, allowing the SHA-3 core to handle diverse input ranges and generate hash outputs based on the selected SHA-3 mode, entirely in hardware without software involvement. A simplified round constant (RC) generator is incorporated in the iota step to reduce slice consumptions. In addition, the proposed hardware architecture has been coarsegrained pipelined to enhance the operating clock frequency. The architecture is implemented on the Virtex 7 FPGA device, demonstrating its speed, efficiency, and adaptability. To the best of the authors' knowledge, this is the first hardware-based design for dynamic input processing in KECCAK, supporting all SHA3 family modes, including XOFs. The design achieves a 25.26% reduction in area, attaining $3.8 \times$ improvement in frequency compared to the latest state-of-the-art design.