Address-Dependent Divided-Bit-Line NAND Flash Memory for Reduction in Latency and Energy

In this paper, we propose an address-dependent divided-bit-line (BL) NAND Flash memory to reduce read latency. Energy consumption in the bit-line path can also be reduced with this design. A single switching MOSFET is added per BL. When a memory cell located closer to the sense amplifier (SA) is selected for reading, the switch is turned off. The SA sees a shorter BL with smaller parasitic capacitance and resistance, resulting in lower latency and reduced energy consumption in the BL path. Conversely, when a memory cell located farther from the SA is selected for reading, the switch is turned on. The SA perceives the original bit-line as long as the on-resistance of the switch is sufficiently low compared to the BL resistance. The average BL access time and energy consumption can be minimized analytically when the switch is placed at $x_{S W}$ of 0.58 and 0.50, respectively, where $x_{S W}$ indicates the switch location ($x_{S W}=0$ at the closest to the SA and $x_{S W}=1$ at the farthest from the SA), assuming that the memory cells are accessed in random. With the proposed design, the average read latency and energy consumption can be reduced to 62% and 75%, respectively. The effectiveness of the proposed design was validated using SPICE simulations. This paper also investigates 1) the scenario where hot memory cells are placed closer to the SA while cold cells are located farther from the SA, and 2) the scenario where multiple switches are built in every BL.